1. Field of the Invention
The invention relates in general to a structure for digital filter devices, and to the method of its operation. In particular, the invention relates to a digital filter bank device employing the principle of decimation in a multi-rate system and the use of a distributed arithmetic algorithm for design simplification and reduction of physical structural dimensions necessary for device implementation, as well as its corresponding method of operation in a time-multiplexed manner.
2. Technical Background
In the processing of audio and/or video signals, such as for speech, music, image and movies, digital signal processors (DSP) are frequently utilized to implement the necessary operations on digital data in processes such as storage into or retrieval out of signal storage media, transmission from a source to a destination, and broadcasting. DSPs are essentially independent processor integrated circuit chips that are driven by firmware programs. These processors are substantially dedicated to the sole purpose of digital signal processing and are therefore more expensive to fabricate. However, a DSP design does not grow physically larger when the signal the DSP processes increases in complexity in terms of, for example, the number and/or category of original signal sources. The complexity of the DSP operation is reflected in the software routines it is required to execute to process the signal.
Another scheme to process audio and/or video signals involves the use of banks of either analog or digital filters (more generally known as filter banks) to sub-divide an input signal into a number of groups of signals, each having a narrower frequency band than the original input. Each of these narrower frequency-band signals is normally derived from the original input signal, based on a general categorization, or on the specific characterization of its respective required processing emphasis.
For example, for an input signal having mixed speech and music sources, the filter-extracted portion of the speech frequency-weighted signal will normally have processing emphasis placed on speed recognition, while the music signal portion will require processing emphasis on musical signal synthesis, in addition to the compression processing required for both. Different signal processing schemes or algorithms will therefore be required in performing specific tasks on the respective portions of the signal derived from the original input by the filter bank device. This approach has an underlying drawback.
The general principle of employing different task-oriented algorithms for individually processing discrete portions of an input signal inevitably requires too many filter components in the filter bank that is used to break down the original input. The larger the number of filter-derived signals, the larger the number of required filters in the filter bank. For digital filters, multipliers, adders, and registers make up the principal building blocks. Unfortunately, a digital multiplier is complicated in structure, much more than either an adder or a register. Therefore, a product of this filter bank processing scheme is a filter bank device that has an excessive die surface area when implemented in a semiconductor device.
The underlying concept of conventional filter banks used in signal processing is briefly examined with reference to FIG. 1. FIG. 1 shows the block diagram of a conventional filter bank that can be used for processing audio and/or video signals. A number, R, of filters FILTER.sub.-- 1-R in the bank have respective inputs tied to a common signal source INPUT.sub.-- SIGNAL. Each of the filters in the bank produces its own version of the filtered output, OUTPUT.sub.-- SIGNAL.sub.-- 1-R, based on the inherent filtering characteristics assigned and built thereinto. Each of the filtered output signals has a frequency band that is narrower than that of the original input signal. In general, the frequency bands of the filtered signals OUTPUT.sub.-- SIGNAL.sub.-- 1-R are non-overlapping, or slightly overlap each other.
Based on differences in filtering characteristics, digital filters may be generally categorized as finite impulse response (FIR) or infinite impulse response (IIR) filters. The theory of operation and characteristics of these digital filters are well known in the art, information regarding which may be found in many text books covering filters and will not be elaborated here except for a brief examination of a drawing to show the principle of the invention. For this purpose, FIG. 2 shows a network diagram of a digital filter having FIR characteristics, and FIG. 3 shows a network diagram of a digital filter having direct form I IIR characteristics, while FIG. 4 shows a network having direct form II IIR characteristics.
As shown in FIGS. 2, 3, and 4, considering a digital filter device, either with the FIR characteristics of FIG. 2 or IIR characteristics of FIG. 3 or 4, having an external input signal represented by X(n) at a time n provided to the input, a filtered signal Y(n) will be generated at the output. In the examples of the IIR digital filters of both FIGS. 3 and 4, a pole signal W(n) is used to signify an intermediate value of the input signal X(n). This is convenient for the mathematical characterization of the filters to be shown in expressions below that utilize a time series to express the filter output Y(n) signal as a function of the input signal X(n).
In the drawings of FIGS. 2, 3, and 4, in which each of the filters is modeled as a network of characterized nodes, let h.sub.0 -h.sub.M, a.sub.1 -a.sub.N-1, b.sub.1 -b.sub.N-1, and c.sub.0 -c.sub.N-1 represent filter characteristic coefficients for the described filter at time n=0, 1, 2, . . . , N-2, and N-1, respectively. In either FIR or IIR filters, a set of expressions express the filter output signal Y(n) at time n as the function of the input signal X(n). Specifically, for the described direct form I IIR digital filter of FIG. 3: EQU W(n)=b.sub.0 .times.X(n)+b.sub.1 .times.X(n-1)+b.sub.2 .times.X(n-2)+ . . . +b.sub.N-1 .times.X(n-(N-1)), (1)
and EQU Y(n)=W(n)+a.sub.1 .times.Y(n-1)+a.sub.2 .times.Y(n-2)+ . . . +a.sub.N-1 .times.Y(n-(N-1)). (2)
Thus, the filter output signal Y(n) at time n may be numerically determined by first evaluating the pole signal value W(n) at the time n in an expression summing a time sequence of products. As shown in the above expression (1) as well as schematically shown in FIG. 3, each of the input signal values X(n-1), X(n-2), . . . , X(n-(N-1)) at points in time previous to n is multiplied by a corresponding coefficient b.sub.0 -b.sub.N-1 and then summed together to obtain the pole signal value W(n) at that particular time. In turn, the filtered output value Y(n) at the same time n may then be determined using expression (2), which also sums a sequence of products. This mathematical modeling characterizes an IIR digital filter as a series of cascaded network nodes, each delayed in time with respect to previous ones and related by a function Z.sup.-1, as is schematically designated in the drawing.
The direct form II IIR digital filter of FIG. 4 may be modeled using similar numerical expressions: EQU W(n)=X(n)+a.sub.1 .times.W(n-1)+a.sub.2 .times.W(n-2)+ . . . +a.sub.N-1 .times.W(n-(N-1)) (3)
and EQU Y(n)=c.sub.0 .times.W(n)+c.sub.1 .times.W(n-1)+c.sub.2 .times.W(n-2)+ . . . +c.sub.N-1 .times.W(n-(N-1)). (4)
The simple time-sequential equations (1) and (2) (as well as (3) and (4)) for numerically determining the filtered signal output value of an IIR digital filter, although straight-forward and easily realized when fabricated on a semiconductor device, are often impractical when actually implemented. This is because a number of digital adders, multipliers, and shift registers are required to perform the numerical evaluations set forth in the equations. The quantity of digital components increases linearly as the order of an implemented filter is increased. When a digital filter bank device is designed utilizing these IIR digital filters to process a signal source having multiple sub-sources of music, speech, video, etc., the total number of adder/multiplier/shift register sets increases to a level barely practical for fabrication in any semiconductor integrated circuit device. The reason for this, as mentioned previously, is that digital multipliers require vast amounts of device die surface area to implement. Thus, the dilemma of this implementation is straight-forward: simple in concept, but impractical in application.